1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to contacts in a liquid crystal display device and a method of fabricating the same.
2. Description of the Related Art
In general, a liquid crystal display (LCD) device controls a light transmittance of liquid crystal cells using an electric field having a dielectric anisotropy, to thereby display a picture. To this end, the LCD device includes a liquid crystal display panel with the liquid crystal cells in an active matrix arrangement, and driving circuits for driving the liquid crystal panel. The liquid crystal display panel includes a common electrode and pixel electrodes to supply the electric field to each of the liquid crystal cells. Usually, each of the pixel electrodes corresponding to a liquid crystal cell is formed on a lower substrate, while the common electrode is integrally formed on the entire surface of an upper substrate. The pixel electrode is connected to a thin film transistor (TFT) that is used as a switching element. The pixel electrode drives the liquid crystal cell jointly with the common electrode, in response to data signals supplied via the TFT. The driving circuit includes a gate driver, a data driver, a timing controller and a power supply. The gate driver drives gate lines of the liquid crystal display panel. The data driver drives the data lines of the liquid crystal display panel. The timing controller controls a driving timing of the gate driver and the data driver. The power supply supplies power signals required for driving the liquid crystal display panel and the driving circuit.
FIG. 1 is a plan view of a liquid crystal display device in accordance with related art. Referring to FIG. 1, a related art liquid crystal display device includes a liquid crystal panel 6; a gate printed circuit board (PCB) 26 and a data PCB 16, a gate tape carrier package (TCP) 8 and a data TCP 12 which are installed between the liquid crystal panel 6 and the gate PCB 26, and the liquid crystal panel 6 and the data PCB 16, respectively, a gate drive integrated circuit (IC) 10 and a data drive IC 14 which are mounted on the gate TCP 8 and the data TCP 12, respectively, a first flexible printed circuit (FPC) 28 that connects the gate PCB 26 and the data PCB 16, a main PCB 20 including the timing controller 22 and the power 24; and a second FPC 18 serving to connect the main PCB 20 and the data PCB 16.
In the liquid crystal panel 6, a liquid crystal cell is arranged in a matrix structure at a pixel region defined between gate lines GL and data lines DL. The liquid crystal panel 6 includes a lower substrate 2 and an upper substrate 4 and is fabricated by injecting liquid crystal material between the lower substrate 2 and the upper substrate 4 and then combining the lower substrate 2 and the upper substrate 4 having the liquid crystal material therebetween. A plurality of gate pads (not shown) is formed at the edge of one side of the lower substrate 2 of the liquid crystal panel 6. A plurality of data pads (not shown) is formed at the edge of a lower portion of the lower substrate 2 of the liquid crystal panel 6.
Each of the gate pads supplies a gate signal from the gate drive IC 10 to the gate lines GL. Also, each of the data pads supplies a data signal from the data drive IC 14 to the data lines DL. The gate pad and the data pad formed on the liquid crystal panel 6 are electrically connected to the gate TCP 8 and the data TCP 12, respectively, by a tape automated bonding (TAB) system.
Each of the gate TCP 8 and the data TCP 12 is made of a polyimide base film on which input and output pads are formed for the connection of input and output parts. The gate drive IC 10 and the data drive 14 are mounted on the gate TCP 8 and the data TCP 12, respectively. The output parts of the gate TCP 8 and the data TCP 12 are connected to the gate pad and the data pad, respectively. The input parts of the gate TCP 8 and the data TCP 12 are connected to the gate PCB 26 and the data PCB 16, respectively.
The gate drive IC 10 is connected to the gate line GL through the gate TCP 8 and the gate pad of the liquid crystal display panel 6. The gate drive IC 10 sequentially supplies a scanning signal having a gate high voltage Vgh to the gate lines GL during a first time interval. Further, the gate drive IC 10 supplies a gate low voltage Vgl to the gate lines GL for a remaining interval excluding the first time interval. To this end, the gate drive IC 10 receives a gate control signal from the timing controller 22 and a power signal from the power 24 on the main PCB 20 via the first FPC 28 and the gate PCB 26.
The data drive IC 14 supplies red, green and blue (R,G,B) data provided from the data PCB 16 to the data lines DL. To this end, the data drive IC 14 receives data control signals, pixel data and power signals from the timing controller 22 and a power signal from the power 24 on the main PCB 20 via the data PCB 16 and the second FPC 18.
FIG. 2 is a detailed plan view of a pad part depicted in FIG. 1. FIG. 3 is a sectional view of the pad part taken along line III-III′ as depicted in FIG. 2. Referring to FIGS. 2 and 3, the data pad includes a lower data pad electrode 40 connected to the data line DL and an upper data pad electrode 42 connected, via a contact hole 41, to the lower data pad electrode 40. The upper data pad electrode 42 is electrically connected to an output pad 58 formed on a base film 60 of the data TCP 12 by a conductive ball 52 of an anisotropic conductive film (ACF) 50.
The ACF 50 is attached on the upper data pad electrode 42 of the liquid crystal display panel 6. Also, the output pad 58 of the data TCP 12 is aligned to overlap the lower data pad electrode 40 and then is pressured by a pressure device 62. Then, the conductive ball 52 included in the ACF 50 is electrically connected to the upper data pad electrode 42. Similarly, in the gate pad (not shown), an output pad of the gate TCP 8 is electrically connected to the upper data pad electrode via the conductive ball of the ACF.
The contact hole employed for the electrical connection of the output pad 58 and the upper data pad electrode 40 is shaped as a bucket shape in accordance with the shape of the lower data pad electrode 40. Although the electrical connection of the output pad 58 and the upper data pad electrode 41 is made by forming the contact hole 41, the distance between the output pad 58 and the upper data pad electrode 42 increases because of the bucket shape of the contact hole 41. Thus, the conductive ball 52 in the ACF 50 would not contribute to the connection between the output pad 58 and the upper data pad electrode 42. Only the contact ball 52 located at a region, which excludes the contact hole 41, substantially contributes to the electrical connection between the pads of the data TCP 12 and the liquid crystal display panel 6. Accordingly, the contact area corresponding to the electrical connection between the output pad of the data TCP 12 and the upper data pad electrode 42 decreases. Thus, a contact between these pads deteriorates. Moreover, a defective contact between these pads causes a deterioration in a picture quality of a liquid crystal display device.